HorvatM is an inexplicable font of information, and has shed some light on many tricky subjects in the past. Today is no different. The subject was tricky enough that neither of us was sure what the right answer was. (-:
The issue is the SETF instruction, which checks for the same conditions as the conditional branch instruction Bcond, but instead of branching, simply stores a 1 in the given register if the condition passes, or a 0 if it fails.
Assembler instructions with a condition code as operand, for example SETF, have this format in the Renesas documentation:
In the IAR assembler, the condition code is merged with the mnemonic:
Sure, it says “syntax deviations” up there, but then why did it appear that way in an official NEC presentation? Further muddying matters is the fact that IAR is an official partner of Renesas, meaning their notation at the very least is officially-ordained.
HorvatM and I came to the same conclusion (for a change (-: ) on the matter: both forms are officially sanctioned, so both forms are valid.